Intel Mobile Communications (India) - Openings

This is closed!!!!! The following are the list of Current Openings:
For most of the opening below Mobile Domain Experience in 2G/CDMA/3G/LTE, · Understanding of Smartphone development and Excellent communication skills are a must.

1. Project Manager/Chief Project Manager (10+ Years Exp.)
2. Storage Device Drivers (3+ Years Exp.)
3. Graphics Drivers (4-10 Years Exp.)
4. Power Drivers (4-10 Years Exp.)
5. Modem Drivers (3-7 Years Exp.)
6. System Debugger (4-6Years Exp.)
7. Concept Engineering (6-9 Years Exp.)
8. CLA (3-6 Years Exp.)
9. MA (4-6 Years Exp.)
10. System Trace Tool (4-6 Years Exp.)
11. HART (4-7 Years Exp.)
12. Configuration Management (7-10 Years Exp.)
13. SE/SSE – Regi Protocol Test (3-5 Years Exp.)
14. Test & Build Automation (3-8 Years Exp.)
15. Driver Testing (3-5 Years Exp.)
16. Modem Testing (3-7 Years Exp.)
17. Functional Project Manager (10-13 Years Exp.)
18. NAS Engineer (3-7 Years Exp.)
19. GAS Engineer (3-7 Years Exp.)
20. UMTS Layer 1 (4 - 9 Years Exp.)
21. AGPS Protocol Dev Engineer (4-8 Years Exp.)
22. AGPS Lead (8+ Years Exp.)
23. AGPS Device Driver (4-8 Years Exp.)
24. Specman Verification (4-8 Years Exp.)
25. IO Design Lead (6-13 Years Exp.)
26. Layout Lead (6-13 Years Exp.)
27. Std Cell Design Lead (6-13 Years Exp.)
28. Std Cell Layout Lead (6-13 Years Exp.)
29. Design Flow Engineer (3-5 Years Exp.)
30. Sysway Flow Engineer (3-5 Years Exp.)

Please send you updated resume directly to jobs [at] digitalelectronics [dot] co [dot] in, with subject line as "Resume for Intel Mobile Communications India - 2011"

For more details about the individual openings please read the comments below or leave a comment. Please don't send enquiries to the email address. They will not be read!

FAE/TSE - Semiconductors - Bangalore

Our client designs and delivers semiconductor and IP solutions which enable their clients to provide maximum signal integrity within their multimedia and communication products.

Description:
• Guide and assist sales staff in assessing potential application of products to meet customer needs.
• Assist customers in selecting correct products or designs. Provide specialized system conceptualization and configuration service.
• Provide follow-up support in disseminating technical information on specific applications.
• Investigate and analyze customer application problems on delivered products to determine problem and any potential liability.
• Prepare documentation for, specialized seminars, application notes, and technical papers.
• Hold seminars to customers to introduce existing and new products.
• Feed back appropriateness of fit of products to customer’s need to Marketing & Applications Engineering.
• Responsible for identifying and clarifying any technical issues related to new or existing products and clearly communicate that to the business unit product lines.

Qualifications & Experience:
• BS/MS in electrical engineering or a comparable technical degree and related work experience.
• Minimum of 5 years of customer facing experience with a preference for candidates from the semi-conductor industry.
• Ability to make technical presentations is required. Strong technical knowledge of datacom communications is required.
• Knowledge of high-speed serial communication ICs for 10Gigabit Ethernet, Fiber Channel, OC-192 SONET, PCIe
• Proven ability to find new business and development strong relationships with customers
• Ability to work in a cross-functional environment with a track record of team participation
• Excellent presentation and communication skills
• Willingness and ability to travel throughout India
• Competency with MS Office (Word, Excel, PowerPoint)

REF: SS5007

If you are interested in the above position, please send us a copy of your up-to-date CV in Word format to laurie@icpsearch.com

Looking for freelancer in SystemVerilog/OVM in Bangalore

A bangalore based MNC is looking for a freelancer in SystemVerilog/OVM.
Please leave a comment with contact details for more info.

Masamb Electronics Pvt. Ltd

Masamb Electronics Pvt. Ltd. as multiple openings in the field of Memory Layout, Characterization for Engineer and Sr. Engineer positions. If you are interested in applying for the same, please reply back with your contact no. or forward your resume at frs@utkrist.com. You can also refer your friends for the same and get referral bonus from SPOG, if they get selected for the job.

The job description is as follows:

Memory Layout: Post: Engineer or Sr.Engineer: Exp:1-5, Location : Noida

Desired Candidate Profile:
* Good experience on Memory layout.
* Basic concept of memory like SRAM,DRAM,bitcell etc and memory compiler.
* Good experience of working on Virtuso LE/XL,calibre/assura,DRC,LVS.
* Knowledge of SKILL and Extraction is a plus

Memory Characterization/Pkg, Post: Engineer or Sr Enginner, Exp: 1-5, Location: Noida

Desired Candidate Profile :
* Good understanding of cmos process & transistor level concepts .
* Knowledge of spice level simulator is most preferred.
* Knowledge of scripting Tcl/Perl is preferred. * Good knowledge of Memory blocks and controllers .
* Knowledge of SRAM, DRAM.
* Experience on memory characterization would be prefered. Tools used:Eldo,HSPICE,spectra.

To refer a friend log on to SPOG website and click refer/apply and provide us their name, email id and phone no.

Regards,
Sunistha
http://spog.utkrist.com/.
frs@utkrist.com
#9972936982

Openings with AMD Bangalore and Hyderabad

Openings with AMD Bangalore and Hyderabad

1. SOC Verification - SMTS / Manager
As an SOC Verification Manager, You will be responsible for leading the verification of next generation Fusion SOC's in the Processor Silicon Engineering (PSE) Group at AMD. This is a hands-on technical management position with tremendous potential for growth and visibility in the organization. Ideal position for a candidate who wants to directly participate and influence the state-of-the-art verification methodologies

Your responsibilities will include, but not limited to:
§       Drive the development of Verification test plans, Coverage metrics, Verification components and Stimulus generation
§       Work closely with Verification Center of Excellence (VCoE) to enable newer verification methodologies and continuous process improvement
§       Work with technical leads in both verification & debug and provide direction on critical decisions
§       Assign resources and schedule tasks per program priorities. Work collaboratively with other functional leads/managers to prioritize deliverables
§       Interact with IP teams globally and ensure the deliverables and schedules are aligned per SOC program goals
§       Track the infrastructure needs – Compute farms and Disk space
§       Provide periodic updates to Program Management on progress and escalate issues on time
§       Mentor and guide the team development, provide performance feedback to the team. Provide career direction to team members
§       Provide strong technical leadership in problem solving and planning

Experience & Skills:
§       10-15 years of experience in IP/SOC verification and atleast 3-5 years of recent experience in leading verification of processor based complex SOCs
§       Possess a Bachelors or Masters degree in Computer Engineering or Electrical Engineering
§       Atleast 2-3 years of direct people management and mentoring
§       Demonstrated successful completion of atleast 1-2 SOC verification projects either as a verification lead or manager
§       Ability to define and track verification metrics for complex verification projects
§       Able to review and critique the verification plans and coverage goals by understanding the SOC system level view and architecture
§       Thorough understanding of state-of-the-art verification methodologies, tools and languages
§       Hands-on working knowledge on any of following; Coverage based verification, Assertion based verification, VMM/OVM, VCS/NCSIM, Debussy, System Verilog
§       C/PERL/TCL and Unix scripting experience is a plus
§       Direct experience on x86 or ARM processor based SOC verification is a plus, but not required
§       Post silicon debug and validation experience is a plus
§       Excellent communication skills and ability to communicate information and ideas succinctly
§       Ability to solve complex problems by reviewing related information to develop and evaluate options and implement solutions

2. SOC Verification – MTS /Sr. Engineer
8 -12 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
Verilog/High level verification
SOC verification and random test generation
Testplanning & test writing especially for processor verification
Exposure to tools like: VCS/NCSim, Debussy
Perl and scripting

Knowledge/exposure to complete SOC tape-out flow

3. SOC Design  - SMTS/Manager
10+ years engineering experience in an IP/SOC product development environment with evidence and willingness of doing Technical Leadership and engineering management of a team of highly skilled engineers
Good university Degree in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience
Should be an expert in CDC/LEDA/RTL/Synthesis. Understanding of low power is a plus
Experience and strong aptitude for Line-Management/People Management
Good understanding of resource management and appreciation for operational aspects such as budgeting, cost management.
Experience in recruitment and team building as well as performance management for engineers
Familiar with Design Verification/validation best practices such as Test Plan development, Testbench development and measurable execution thereof
Familiar with Microprocessor and/or SoC Architecture
Planning and coordination of resources and team members to meet SoC Design/Implementation goals on time and within budget
Ensure that requirements are accurately transferred into a meaningful engineering project. Determine appropriate timescales, provide project plans and appropriate input to specifications, and use the assigned engineering resource creatively to ensure that all engineering commitments are delivered successfully
Maintain a competent knowledge of company processes in order to work constructively within given standards and methodologies
Monitor inter-project dependencies and risks, assist in the resolution of differences where necessary, to achieve greater success.
Work with stakeholders; informing, communicating progress and managing expectations.

4. SOC Design  - MTS
 8–10 yrs of experience

Candidate should posses good mix of front end skills with a good working experience on power estimation and low power design techniques.
• Sound knowledge of low power methodology and power estimation procedures
• Working experience with power estimation tools (Power Theater/PT-PX) and CLP flow
• Hands on experience with Low power methodologies using UPF/CPF
• Needs to have sound fundamentals in RTL design and micro architecture
• Needs hands on experience with LEC/Lint/CDC
• Good understanding on Synthesis/STA flows
• Good Perl/TCL scripting skills
• Experience working with global teams

5. Program Manager Fusion SOC
Job Description: As a Program Manager in the Processor solutions Engineering (PSE) Team you will be responsible for helping drive our next generation fusion SOC programs.

Responsibilities will include:
§       Defining and managing key product deliverables/schedules and driving cross functional activities
§       Managing horizontally across several functional organizations is a key job function
§       Working hand-in-hand with engineering counterparts across the global sites to plan/align IP schedules and delivery, extensive interactions within the PSE SOC organization to ensure alignment of program goals
§       Support in the development of project plans, schedules, and must be able to develop and improve processes for project tracking and risk mitigation
§       Support the Engineering management in planning of project Human and Computing resource needs
§       Support Engineering management to drive execution excellence, including key metrics like Time-to-Market, R&D Efficiency, and Silicon Quality Indicators
§       Work collaboratively with the AMD Program Management community to track Key metrics and help continuous process improvement.
§       Interpret/understand business directions, explaining tactical details, and recommending solutions regarding complex program situations

Experience & Skill Set:

B.E/B.Tech, or M.E/M.Tech in Engineering (EE, Computer Science)
10+ years Project Management experience in  industry

PMP certification is a plus, but not required

Good presentation and leadership skills; with ability to lead technical discussions

Strong interpersonal skills

Outstanding written and oral communication skills

Experience in managing complex, interrelated projects, programs, and functions

Hands-on experience in IP/SOC development in any functional area; Design Verification, Design Integration, Physical design and Post silicon validation

Working knowledge across multiple engineering disciplines (i.e. Boards, Thermal, Packaging, Process Technology, Product Engineering, Software) is desirable

Team player with a commitment to meeting deadlines and an aptitude to thrive in a fast paced multi-tasking environment

SoC/Processor Verification: 4+ years

Preferred Education and experience: The Candidate should have a Master's with 5+ years of experience or Bachelor of Engineering with 7+ years of experience in electronics or Computer engineering. Experience in large ASIC or processor design/verification, SoC/Processor architecture and micro architecture, C/C++ programming language, scripting languages, and simulation and debug tools is a must. Candidate should have experience in SoC Verification a large ASIC/Processor, design and debug using Verilog/system Verilog (or equivalent HVL).  Processor verification experience is an added advantage. Ability to technically lead a team of highly skilled engineers.

Primary Purpose: Primary job function is to provide technical leadership to the verification team and own/drive one or more area/feature verification at full chip level and meet grade level expectations

Key Job Functions: Own and verify one or more area/feature at full chip level. Play a driving role in verification environment development (detailed test plans, checkers, irritators, models, stimuli), debug and root cause failures and innovation in SoC verification work flow. Providing technical leadership to junior engineers in the team including mentorship. Represent verification team in various forums and work with overseas teams. Good team work to ensure timely and quality deliverables. Meet grade level expectations (technical leadership, innovation, supervision requirement, ownership, problem solving, mentoring).

Job Location: Bangalore, Hyderabad

Please revert back with your interest in it ASAP with the following details

CTC:
ECTC:
NP:
Mobile No:
Alt Mail ID:
2 Professional References (Please do mention Email ID and Contact No:

Thanks & Regards,
Sailaja.K
Techpoint Solutions Pvt Ltd
040-44354435
mailto:sailaja@techpointsolutions.com

MTS Engineer- AMSCOE Verification

Job Description:  IP verification MTS Engineer is responsible to lead the Pre Silicon verification team for the timely delivery the good Quality of RTL and Gates to the consumers and also work on design Enhancements and methodology improvements to upgrade the Quality metrics. 

Job Responsibilities: 

This candidate is responsible to lead a verification team for an IP block and closely working with Design/Architecture/Circuit team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery. He/She would be reviewing the day-day team’s activities on developing verification test bench activities such as feature scoping, test case development, Infrastructure enhancements, coverage and debug efforts. He/She will also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment. Also driving and participating pre silicon Verification discussions across other functional engineering team geographically.

 Relevant Experience:

• BE/B.Tech with 8 to 12 years of experience or M.E/M.Tech with 6 to 10 years of experience in Pre silicon verification out of which 3 years in Technical leadership position.
• Minimum 6 years of relevant experience in RTL Verification of complex logic blocks in processor, chipset, networking domain is essential.
• Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification.
• Needs to have better understanding of Verification methodology and concepts.
• Should have excellent communication skills (both written and oral) and should be able to participate and drive cross functional engineering teams geographically.
• Must have worked in verification of few multi-million gate projects either at unit , cluster or top level.
• Must have better programming knowledge on Verilog,C++.
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Knowledge of memory controller (along with domain knowledge of DDR) sub-system is a desirable.(for DDR)
• Analog design knowledge such as transistors, circuit models are desirable. Should have better understanding of Gatesim, Nanasim tools and methodology (for AMS).

Contact: rajsree@techpointsolutions.com

Design & Verification

· 3-10 years of experience in Verilog/VHDL design, analysis and verification of DSP functions
· Developing block level micro-architecture of DSP blocks from algorithms specified in C
· Use HDL for logic design; perform synthesis, static timing analysis & power estimation of the design
· Create self generating / self checking simulation verification environment using C, HDL, Perl scripts
· Be familiar with Verilog and Synopsys tools (VCS, DC, Power Compiler)
· Successful experience in 802.11 Wireless VLSI designs or other related technologies is a plus
· Education: BE/Btech/ME/MTech

Contact:
For more details please contact, Asesh @ 9916784464, E-mail: v.asesh@neweraindia.com

Lattice Semiconductor - Applications Engineer-High Density

Experience : 1 - 2 Years
Location : Bengaluru/Bangalore
Education : UG - B.Sc - Electronics,B.Tech/B.E. - Electrical, Electronics/Telecomunication
PG - Any PG Course - Any Specialization,Post Graduation Not Required
Industry Type : Semiconductors/ Electronics
Functional Area : Engineering Design, R&D

Job Description:
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. We design and develop programmable logic products, which allow the end customer to determine functionality. Our customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets. Not only does Lattice offer unparallel product portfolios in a very competitive industry, but it also offers a fantastic working environment that allows the employee’s unique individuality to flourish. Consider working for a mid-size company with a small-size mentality, each employee has the opportunity to make a direct impact on the company’s successes.

Job Summary:
Lattice's Enterprise Solutions Applications Engineering team is a very uniq! ue and multifaceted group within Lattice. The Applications group is tasked with supporting the majority of Lattice's hardware and software products by working extensively with our customers, and our sales organization. To facilitate this support, the group must also interface with most of the design and development groups in the company. Responsibilities will involve working with Lattice's sale's organization to support customer hardware and software design issues. This will lead to involvement in the development of support related documentation, hardware and software.

Lattice is looking for an Entry Level Applications Engineer to join this team with the following responsibilities:

• Provide engineering and technical marketing support to field sales, field applications and customers.
• Support application hotline for specific product lines. Provide assistance to customers with technical problems.
• Conduct tests to evaluate customer problems.
• Generate and coordinate technical literature, articles, application notes and data sheets.
• Coordinate hardware failure verifications.
• Perform software benchmarking and competitive hardware analysis.
• Perform FPGA logic design using VHDL and Verilog.
• Provide follow-up support in disseminating technical information on specific applications.

Desired Candidate Profile

Qualifications:
• BTech/Mtech/ME/MSc in Electronics and Telecom or equivalent.
• Experience in digital logic design using FPGAs.
• Experience with VHDL and Verilog.
• Knowledge of C and C++.
• Understanding of telecom/datacom systems.
• Customer support experience preferred.
• Strong written and verbal communication skills and the ability to work with multiple groups.
• Must be detail oriented with strong customer service skills.
• High level of PC skills with knowledge of MS Office Suite.
• Experience in telecommunications, wireless and networking helpful.
• Experience with system design and applications engineering helpful.

Their total compensation package includes a comprehensive medical and dental insurance plan, 401K match, employee stock purchase plan and 3 weeks of vacation.

Company Profile
Lattice Semiconductor is one of the world's leading designers of programmable logic technology. NASDAQ-listed, with around 700 employees worldwide, our future has never looked more promising. We are an equal opportunity employer. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

For more information please visit 
 https://www4.ultirecruit.com/LAT1001/JobBoard/listjobs.aspx

Contract Verification Engineers

Design Verification Engineers, Contract opportunities in Texas and NorthEastern US. 3+ years industry experience. US residents or valid visa required.

Key Job Functions:
Develop environments for complex functional verification and debug both
functional and environmental errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design. Develop an automated regression infrastructure setup for functional verification of high speed processor type designs. Develop/run directed tests for current and new functional features and develop/use random excercisors, to validate functionality of processor type system designs. Debug regression fails at the RTL and gate level.
Software infrastructure for validation of architecture correctness.
Directed and Random functional test environment development and use
Experience with functional/power/performance verification using
simulation and emulation environments
Create test plans for complex IPs include multiple processors
Developing test benches in OVM, SystemVerilog and/or C++, applying
pseudo-random test generators, developing System Verilog/C/assembly tests,
analyzing coverage and design-for-test on next generation SOC chip
projects.
Knowledge with Verilog SystemVerilog, HDL, programming in Perl, C/C++,
logic simulation is a requirement. Direct experience with OVM simulation
environment is a strong plus. Knowledge of computer and peripheral
architectures is also required.

contact: Kathy@Xpeerant.com

Job Opportunity with US Based Product Development Company, Bangalore

Work as part of the Design Technology team to be part of development and support of digital IP designs to Product Company worldwide design teams. Primary responsibility includes build new digital IP components, support & maintenance of all digital IPs in the library, support design & implementation teams in different testchip programs in IP integration aspects.

Job functions include:
-Creation of verilog based RTL design, including micro-architecture definition and coding for DFT, synthesis rule compliance.
-Drive IP use model, revision control process and manage the IP release process to different design teams.
-Support bug fixes, design enhancements to keep all the IPs in library up-to-date.
-Work closely with verification team to ensure that exhaustive verification all IPs are done.
-Creating documentation to aid easy re-use of IP
-Work closely with the circuit, logic and implementation teams and support re-use & customization of IP.

Requirements:
-Bachelors or Masters in Electrical / Electronic Engineering with at least 3-4 years of experience in IP development and integration support.
-Hands on experience in Verilog based digital design creation.
-Prior memory technology (DDRx / GDDRx / LPDDRx) experience preferred.  
-Exposure to scripting/programming ability using PERL, MAKEFILE.
-Good familiarity with usage of configuration management systems (any one of: DesignSync, ClearCase, Perforce, ICManage
-Hands on experience / support in tape-out of at least two chips would be added advantage.

Abilities:
-Work effectively and independently in a multi-site, multi-cultural environment
-Self-motivated team player with strong organizational, time management and communication skills.

Note: we will process your CV with your due Consent Only
Do send your Update CV & Please mention below details

Current CTC:
Expected CTC:
Duration for Joining:
Current Location:
Location Preference:

contact: nalini@techpointsolutions.com