A bangalore based MNC is looking for a freelancer in SystemVerilog/OVM.
Please leave a comment with contact details for more info.
Wednesday, December 1, 2010
Monday, November 1, 2010
Masamb Electronics Pvt. Ltd
Masamb Electronics Pvt. Ltd. as multiple openings in the field of Memory Layout, Characterization for Engineer and Sr. Engineer positions. If you are interested in applying for the same, please reply back with your contact no. or forward your resume at frs@utkrist.com. You can also refer your friends for the same and get referral bonus from SPOG, if they get selected for the job.
The job description is as follows:
Memory Layout: Post: Engineer or Sr.Engineer: Exp:1-5, Location : Noida
Desired Candidate Profile:
* Good experience on Memory layout.
* Basic concept of memory like SRAM,DRAM,bitcell etc and memory compiler.
* Good experience of working on Virtuso LE/XL,calibre/assura,DRC,LVS.
* Knowledge of SKILL and Extraction is a plus
Memory Characterization/Pkg, Post: Engineer or Sr Enginner, Exp: 1-5, Location: Noida
Desired Candidate Profile :
* Good understanding of cmos process & transistor level concepts .
* Knowledge of spice level simulator is most preferred.
* Knowledge of scripting Tcl/Perl is preferred. * Good knowledge of Memory blocks and controllers .
* Knowledge of SRAM, DRAM.
* Experience on memory characterization would be prefered. Tools used:Eldo,HSPICE,spectra.
To refer a friend log on to SPOG website and click refer/apply and provide us their name, email id and phone no.
Regards,
Sunistha
http://spog.utkrist.com/.
frs@utkrist.com
#9972936982
The job description is as follows:
Memory Layout: Post: Engineer or Sr.Engineer: Exp:1-5, Location : Noida
Desired Candidate Profile:
* Good experience on Memory layout.
* Basic concept of memory like SRAM,DRAM,bitcell etc and memory compiler.
* Good experience of working on Virtuso LE/XL,calibre/assura,DRC,LVS.
* Knowledge of SKILL and Extraction is a plus
Memory Characterization/Pkg, Post: Engineer or Sr Enginner, Exp: 1-5, Location: Noida
Desired Candidate Profile :
* Good understanding of cmos process & transistor level concepts .
* Knowledge of spice level simulator is most preferred.
* Knowledge of scripting Tcl/Perl is preferred. * Good knowledge of Memory blocks and controllers .
* Knowledge of SRAM, DRAM.
* Experience on memory characterization would be prefered. Tools used:Eldo,HSPICE,spectra.
To refer a friend log on to SPOG website and click refer/apply and provide us their name, email id and phone no.
Regards,
Sunistha
http://spog.utkrist.com/.
frs@utkrist.com
#9972936982
Openings with AMD Bangalore and Hyderabad
Openings with AMD Bangalore and Hyderabad
1. SOC Verification - SMTS / Manager
As an SOC Verification Manager, You will be responsible for leading the verification of next generation Fusion SOC's in the Processor Silicon Engineering (PSE) Group at AMD. This is a hands-on technical management position with tremendous potential for growth and visibility in the organization. Ideal position for a candidate who wants to directly participate and influence the state-of-the-art verification methodologies
Your responsibilities will include, but not limited to:
§ Drive the development of Verification test plans, Coverage metrics, Verification components and Stimulus generation
§ Work closely with Verification Center of Excellence (VCoE) to enable newer verification methodologies and continuous process improvement
§ Work with technical leads in both verification & debug and provide direction on critical decisions
§ Assign resources and schedule tasks per program priorities. Work collaboratively with other functional leads/managers to prioritize deliverables
§ Interact with IP teams globally and ensure the deliverables and schedules are aligned per SOC program goals
§ Track the infrastructure needs – Compute farms and Disk space
§ Provide periodic updates to Program Management on progress and escalate issues on time
§ Mentor and guide the team development, provide performance feedback to the team. Provide career direction to team members
§ Provide strong technical leadership in problem solving and planning
Experience & Skills:
§ 10-15 years of experience in IP/SOC verification and atleast 3-5 years of recent experience in leading verification of processor based complex SOCs
§ Possess a Bachelors or Masters degree in Computer Engineering or Electrical Engineering
§ Atleast 2-3 years of direct people management and mentoring
§ Demonstrated successful completion of atleast 1-2 SOC verification projects either as a verification lead or manager
§ Ability to define and track verification metrics for complex verification projects
§ Able to review and critique the verification plans and coverage goals by understanding the SOC system level view and architecture
§ Thorough understanding of state-of-the-art verification methodologies, tools and languages
§ Hands-on working knowledge on any of following; Coverage based verification, Assertion based verification, VMM/OVM, VCS/NCSIM, Debussy, System Verilog
§ C/PERL/TCL and Unix scripting experience is a plus
§ Direct experience on x86 or ARM processor based SOC verification is a plus, but not required
§ Post silicon debug and validation experience is a plus
§ Excellent communication skills and ability to communicate information and ideas succinctly
§ Ability to solve complex problems by reviewing related information to develop and evaluate options and implement solutions
2. SOC Verification – MTS /Sr. Engineer
8 -12 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
Verilog/High level verification
SOC verification and random test generation
Testplanning & test writing especially for processor verification
Exposure to tools like: VCS/NCSim, Debussy
Perl and scripting
Knowledge/exposure to complete SOC tape-out flow
3. SOC Design - SMTS/Manager
10+ years engineering experience in an IP/SOC product development environment with evidence and willingness of doing Technical Leadership and engineering management of a team of highly skilled engineers
Good university Degree in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience
Should be an expert in CDC/LEDA/RTL/Synthesis. Understanding of low power is a plus
Experience and strong aptitude for Line-Management/People Management
Good understanding of resource management and appreciation for operational aspects such as budgeting, cost management.
Experience in recruitment and team building as well as performance management for engineers
Familiar with Design Verification/validation best practices such as Test Plan development, Testbench development and measurable execution thereof
Familiar with Microprocessor and/or SoC Architecture
Planning and coordination of resources and team members to meet SoC Design/Implementation goals on time and within budget
Ensure that requirements are accurately transferred into a meaningful engineering project. Determine appropriate timescales, provide project plans and appropriate input to specifications, and use the assigned engineering resource creatively to ensure that all engineering commitments are delivered successfully
Maintain a competent knowledge of company processes in order to work constructively within given standards and methodologies
Monitor inter-project dependencies and risks, assist in the resolution of differences where necessary, to achieve greater success.
Work with stakeholders; informing, communicating progress and managing expectations.
4. SOC Design - MTS
8–10 yrs of experience
Candidate should posses good mix of front end skills with a good working experience on power estimation and low power design techniques.
• Sound knowledge of low power methodology and power estimation procedures
• Working experience with power estimation tools (Power Theater/PT-PX) and CLP flow
• Hands on experience with Low power methodologies using UPF/CPF
• Needs to have sound fundamentals in RTL design and micro architecture
• Needs hands on experience with LEC/Lint/CDC
• Good understanding on Synthesis/STA flows
• Good Perl/TCL scripting skills
• Experience working with global teams
5. Program Manager Fusion SOC
Job Description: As a Program Manager in the Processor solutions Engineering (PSE) Team you will be responsible for helping drive our next generation fusion SOC programs.
Responsibilities will include:
§ Defining and managing key product deliverables/schedules and driving cross functional activities
§ Managing horizontally across several functional organizations is a key job function
§ Working hand-in-hand with engineering counterparts across the global sites to plan/align IP schedules and delivery, extensive interactions within the PSE SOC organization to ensure alignment of program goals
§ Support in the development of project plans, schedules, and must be able to develop and improve processes for project tracking and risk mitigation
§ Support the Engineering management in planning of project Human and Computing resource needs
§ Support Engineering management to drive execution excellence, including key metrics like Time-to-Market, R&D Efficiency, and Silicon Quality Indicators
§ Work collaboratively with the AMD Program Management community to track Key metrics and help continuous process improvement.
§ Interpret/understand business directions, explaining tactical details, and recommending solutions regarding complex program situations
Experience & Skill Set:
B.E/B.Tech, or M.E/M.Tech in Engineering (EE, Computer Science)
10+ years Project Management experience in industry
PMP certification is a plus, but not required
Good presentation and leadership skills; with ability to lead technical discussions
Strong interpersonal skills
Outstanding written and oral communication skills
Experience in managing complex, interrelated projects, programs, and functions
Hands-on experience in IP/SOC development in any functional area; Design Verification, Design Integration, Physical design and Post silicon validation
Working knowledge across multiple engineering disciplines (i.e. Boards, Thermal, Packaging, Process Technology, Product Engineering, Software) is desirable
Team player with a commitment to meeting deadlines and an aptitude to thrive in a fast paced multi-tasking environment
SoC/Processor Verification: 4+ years
Preferred Education and experience: The Candidate should have a Master's with 5+ years of experience or Bachelor of Engineering with 7+ years of experience in electronics or Computer engineering. Experience in large ASIC or processor design/verification, SoC/Processor architecture and micro architecture, C/C++ programming language, scripting languages, and simulation and debug tools is a must. Candidate should have experience in SoC Verification a large ASIC/Processor, design and debug using Verilog/system Verilog (or equivalent HVL). Processor verification experience is an added advantage. Ability to technically lead a team of highly skilled engineers.
Primary Purpose: Primary job function is to provide technical leadership to the verification team and own/drive one or more area/feature verification at full chip level and meet grade level expectations
Key Job Functions: Own and verify one or more area/feature at full chip level. Play a driving role in verification environment development (detailed test plans, checkers, irritators, models, stimuli), debug and root cause failures and innovation in SoC verification work flow. Providing technical leadership to junior engineers in the team including mentorship. Represent verification team in various forums and work with overseas teams. Good team work to ensure timely and quality deliverables. Meet grade level expectations (technical leadership, innovation, supervision requirement, ownership, problem solving, mentoring).
Job Location: Bangalore, Hyderabad
Please revert back with your interest in it ASAP with the following details
CTC:
ECTC:
NP:
Mobile No:
Alt Mail ID:
2 Professional References (Please do mention Email ID and Contact No:
Thanks & Regards,
Sailaja.K
Techpoint Solutions Pvt Ltd
040-44354435
mailto:sailaja@techpointsolutions.com
1. SOC Verification - SMTS / Manager
As an SOC Verification Manager, You will be responsible for leading the verification of next generation Fusion SOC's in the Processor Silicon Engineering (PSE) Group at AMD. This is a hands-on technical management position with tremendous potential for growth and visibility in the organization. Ideal position for a candidate who wants to directly participate and influence the state-of-the-art verification methodologies
Your responsibilities will include, but not limited to:
§ Drive the development of Verification test plans, Coverage metrics, Verification components and Stimulus generation
§ Work closely with Verification Center of Excellence (VCoE) to enable newer verification methodologies and continuous process improvement
§ Work with technical leads in both verification & debug and provide direction on critical decisions
§ Assign resources and schedule tasks per program priorities. Work collaboratively with other functional leads/managers to prioritize deliverables
§ Interact with IP teams globally and ensure the deliverables and schedules are aligned per SOC program goals
§ Track the infrastructure needs – Compute farms and Disk space
§ Provide periodic updates to Program Management on progress and escalate issues on time
§ Mentor and guide the team development, provide performance feedback to the team. Provide career direction to team members
§ Provide strong technical leadership in problem solving and planning
Experience & Skills:
§ 10-15 years of experience in IP/SOC verification and atleast 3-5 years of recent experience in leading verification of processor based complex SOCs
§ Possess a Bachelors or Masters degree in Computer Engineering or Electrical Engineering
§ Atleast 2-3 years of direct people management and mentoring
§ Demonstrated successful completion of atleast 1-2 SOC verification projects either as a verification lead or manager
§ Ability to define and track verification metrics for complex verification projects
§ Able to review and critique the verification plans and coverage goals by understanding the SOC system level view and architecture
§ Thorough understanding of state-of-the-art verification methodologies, tools and languages
§ Hands-on working knowledge on any of following; Coverage based verification, Assertion based verification, VMM/OVM, VCS/NCSIM, Debussy, System Verilog
§ C/PERL/TCL and Unix scripting experience is a plus
§ Direct experience on x86 or ARM processor based SOC verification is a plus, but not required
§ Post silicon debug and validation experience is a plus
§ Excellent communication skills and ability to communicate information and ideas succinctly
§ Ability to solve complex problems by reviewing related information to develop and evaluate options and implement solutions
2. SOC Verification – MTS /Sr. Engineer
8 -12 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
Verilog/High level verification
SOC verification and random test generation
Testplanning & test writing especially for processor verification
Exposure to tools like: VCS/NCSim, Debussy
Perl and scripting
Knowledge/exposure to complete SOC tape-out flow
3. SOC Design - SMTS/Manager
10+ years engineering experience in an IP/SOC product development environment with evidence and willingness of doing Technical Leadership and engineering management of a team of highly skilled engineers
Good university Degree in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience
Should be an expert in CDC/LEDA/RTL/Synthesis. Understanding of low power is a plus
Experience and strong aptitude for Line-Management/People Management
Good understanding of resource management and appreciation for operational aspects such as budgeting, cost management.
Experience in recruitment and team building as well as performance management for engineers
Familiar with Design Verification/validation best practices such as Test Plan development, Testbench development and measurable execution thereof
Familiar with Microprocessor and/or SoC Architecture
Planning and coordination of resources and team members to meet SoC Design/Implementation goals on time and within budget
Ensure that requirements are accurately transferred into a meaningful engineering project. Determine appropriate timescales, provide project plans and appropriate input to specifications, and use the assigned engineering resource creatively to ensure that all engineering commitments are delivered successfully
Maintain a competent knowledge of company processes in order to work constructively within given standards and methodologies
Monitor inter-project dependencies and risks, assist in the resolution of differences where necessary, to achieve greater success.
Work with stakeholders; informing, communicating progress and managing expectations.
4. SOC Design - MTS
8–10 yrs of experience
Candidate should posses good mix of front end skills with a good working experience on power estimation and low power design techniques.
• Sound knowledge of low power methodology and power estimation procedures
• Working experience with power estimation tools (Power Theater/PT-PX) and CLP flow
• Hands on experience with Low power methodologies using UPF/CPF
• Needs to have sound fundamentals in RTL design and micro architecture
• Needs hands on experience with LEC/Lint/CDC
• Good understanding on Synthesis/STA flows
• Good Perl/TCL scripting skills
• Experience working with global teams
5. Program Manager Fusion SOC
Job Description: As a Program Manager in the Processor solutions Engineering (PSE) Team you will be responsible for helping drive our next generation fusion SOC programs.
Responsibilities will include:
§ Defining and managing key product deliverables/schedules and driving cross functional activities
§ Managing horizontally across several functional organizations is a key job function
§ Working hand-in-hand with engineering counterparts across the global sites to plan/align IP schedules and delivery, extensive interactions within the PSE SOC organization to ensure alignment of program goals
§ Support in the development of project plans, schedules, and must be able to develop and improve processes for project tracking and risk mitigation
§ Support the Engineering management in planning of project Human and Computing resource needs
§ Support Engineering management to drive execution excellence, including key metrics like Time-to-Market, R&D Efficiency, and Silicon Quality Indicators
§ Work collaboratively with the AMD Program Management community to track Key metrics and help continuous process improvement.
§ Interpret/understand business directions, explaining tactical details, and recommending solutions regarding complex program situations
Experience & Skill Set:
B.E/B.Tech, or M.E/M.Tech in Engineering (EE, Computer Science)
10+ years Project Management experience in industry
PMP certification is a plus, but not required
Good presentation and leadership skills; with ability to lead technical discussions
Strong interpersonal skills
Outstanding written and oral communication skills
Experience in managing complex, interrelated projects, programs, and functions
Hands-on experience in IP/SOC development in any functional area; Design Verification, Design Integration, Physical design and Post silicon validation
Working knowledge across multiple engineering disciplines (i.e. Boards, Thermal, Packaging, Process Technology, Product Engineering, Software) is desirable
Team player with a commitment to meeting deadlines and an aptitude to thrive in a fast paced multi-tasking environment
SoC/Processor Verification: 4+ years
Preferred Education and experience: The Candidate should have a Master's with 5+ years of experience or Bachelor of Engineering with 7+ years of experience in electronics or Computer engineering. Experience in large ASIC or processor design/verification, SoC/Processor architecture and micro architecture, C/C++ programming language, scripting languages, and simulation and debug tools is a must. Candidate should have experience in SoC Verification a large ASIC/Processor, design and debug using Verilog/system Verilog (or equivalent HVL). Processor verification experience is an added advantage. Ability to technically lead a team of highly skilled engineers.
Primary Purpose: Primary job function is to provide technical leadership to the verification team and own/drive one or more area/feature verification at full chip level and meet grade level expectations
Key Job Functions: Own and verify one or more area/feature at full chip level. Play a driving role in verification environment development (detailed test plans, checkers, irritators, models, stimuli), debug and root cause failures and innovation in SoC verification work flow. Providing technical leadership to junior engineers in the team including mentorship. Represent verification team in various forums and work with overseas teams. Good team work to ensure timely and quality deliverables. Meet grade level expectations (technical leadership, innovation, supervision requirement, ownership, problem solving, mentoring).
Job Location: Bangalore, Hyderabad
Please revert back with your interest in it ASAP with the following details
CTC:
ECTC:
NP:
Mobile No:
Alt Mail ID:
2 Professional References (Please do mention Email ID and Contact No:
Thanks & Regards,
Sailaja.K
Techpoint Solutions Pvt Ltd
040-44354435
mailto:sailaja@techpointsolutions.com
Wednesday, September 29, 2010
MTS Engineer- AMSCOE Verification
Job Description: IP verification MTS Engineer is responsible to lead the Pre Silicon verification team for the timely delivery the good Quality of RTL and Gates to the consumers and also work on design Enhancements and methodology improvements to upgrade the Quality metrics.
Job Responsibilities:
This candidate is responsible to lead a verification team for an IP block and closely working with Design/Architecture/Circuit team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery. He/She would be reviewing the day-day team’s activities on developing verification test bench activities such as feature scoping, test case development, Infrastructure enhancements, coverage and debug efforts. He/She will also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment. Also driving and participating pre silicon Verification discussions across other functional engineering team geographically.
Relevant Experience:
- BE/B.Tech with 8 to 12 years of experience or M.E/M.Tech with 6 to 10 years of experience in Pre silicon verification out of which 3 years in Technical leadership position.
- Minimum 6 years of relevant experience in RTL Verification of complex logic blocks in processor, chipset, networking domain is essential.
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification.
- Needs to have better understanding of Verification methodology and concepts.
- Should have excellent communication skills (both written and oral) and should be able to participate and drive cross functional engineering teams geographically.
- Must have worked in verification of few multi-million gate projects either at unit , cluster or top level.
- Must have better programming knowledge on Verilog,C++.
- Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
- Knowledge of memory controller (along with domain knowledge of DDR) sub-system is a desirable.(for DDR)
- Analog design knowledge such as transistors, circuit models are desirable. Should have better understanding of Gatesim, Nanasim tools and methodology (for AMS).
Contact: rajsree@techpointsolutions.com
Design & Verification
· 3-10 years of experience in Verilog/VHDL design, analysis and verification of DSP functions
· Developing block level micro-architecture of DSP blocks from algorithms specified in C
· Use HDL for logic design; perform synthesis, static timing analysis & power estimation of the design
· Create self generating / self checking simulation verification environment using C, HDL, Perl scripts
· Be familiar with Verilog and Synopsys tools (VCS, DC, Power Compiler)
· Successful experience in 802.11 Wireless VLSI designs or other related technologies is a plus
· Education: BE/Btech/ME/MTech
Contact:
For more details please contact, Asesh @ 9916784464, E-mail: v.asesh@neweraindia.com
· Developing block level micro-architecture of DSP blocks from algorithms specified in C
· Use HDL for logic design; perform synthesis, static timing analysis & power estimation of the design
· Create self generating / self checking simulation verification environment using C, HDL, Perl scripts
· Be familiar with Verilog and Synopsys tools (VCS, DC, Power Compiler)
· Successful experience in 802.11 Wireless VLSI designs or other related technologies is a plus
· Education: BE/Btech/ME/MTech
Contact:
For more details please contact, Asesh @ 9916784464, E-mail: v.asesh@neweraindia.com
Wednesday, June 30, 2010
Lattice Semiconductor - Applications Engineer-High Density
Experience : 1 - 2 Years
Location : Bengaluru/Bangalore
Education : UG - B.Sc - Electronics,B.Tech/B.E. - Electrical, Electronics/Telecomunication
PG - Any PG Course - Any Specialization,Post Graduation Not Required
Industry Type : Semiconductors/ Electronics
Functional Area : Engineering Design, R&D
Job Description:
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. We design and develop programmable logic products, which allow the end customer to determine functionality. Our customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets. Not only does Lattice offer unparallel product portfolios in a very competitive industry, but it also offers a fantastic working environment that allows the employee’s unique individuality to flourish. Consider working for a mid-size company with a small-size mentality, each employee has the opportunity to make a direct impact on the company’s successes.
Job Summary:
Lattice's Enterprise Solutions Applications Engineering team is a very uniq! ue and multifaceted group within Lattice. The Applications group is tasked with supporting the majority of Lattice's hardware and software products by working extensively with our customers, and our sales organization. To facilitate this support, the group must also interface with most of the design and development groups in the company. Responsibilities will involve working with Lattice's sale's organization to support customer hardware and software design issues. This will lead to involvement in the development of support related documentation, hardware and software.
Lattice is looking for an Entry Level Applications Engineer to join this team with the following responsibilities:
• Provide engineering and technical marketing support to field sales, field applications and customers.
• Support application hotline for specific product lines. Provide assistance to customers with technical problems.
• Conduct tests to evaluate customer problems.
• Generate and coordinate technical literature, articles, application notes and data sheets.
• Coordinate hardware failure verifications.
• Perform software benchmarking and competitive hardware analysis.
• Perform FPGA logic design using VHDL and Verilog.
• Provide follow-up support in disseminating technical information on specific applications.
Desired Candidate Profile
Qualifications:
• BTech/Mtech/ME/MSc in Electronics and Telecom or equivalent.
• Experience in digital logic design using FPGAs.
• Experience with VHDL and Verilog.
• Knowledge of C and C++.
• Understanding of telecom/datacom systems.
• Customer support experience preferred.
• Strong written and verbal communication skills and the ability to work with multiple groups.
• Must be detail oriented with strong customer service skills.
• High level of PC skills with knowledge of MS Office Suite.
• Experience in telecommunications, wireless and networking helpful.
• Experience with system design and applications engineering helpful.
Their total compensation package includes a comprehensive medical and dental insurance plan, 401K match, employee stock purchase plan and 3 weeks of vacation.
Company Profile
Lattice Semiconductor is one of the world's leading designers of programmable logic technology. NASDAQ-listed, with around 700 employees worldwide, our future has never looked more promising. We are an equal opportunity employer. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
For more information please visit
https://www4.ultirecruit.
Location : Bengaluru/Bangalore
Education : UG - B.Sc - Electronics,B.Tech/B.E. - Electrical, Electronics/Telecomunication
PG - Any PG Course - Any Specialization,Post Graduation Not Required
Industry Type : Semiconductors/ Electronics
Functional Area : Engineering Design, R&D
Job Description:
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. We design and develop programmable logic products, which allow the end customer to determine functionality. Our customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets. Not only does Lattice offer unparallel product portfolios in a very competitive industry, but it also offers a fantastic working environment that allows the employee’s unique individuality to flourish. Consider working for a mid-size company with a small-size mentality, each employee has the opportunity to make a direct impact on the company’s successes.
Job Summary:
Lattice's Enterprise Solutions Applications Engineering team is a very uniq! ue and multifaceted group within Lattice. The Applications group is tasked with supporting the majority of Lattice's hardware and software products by working extensively with our customers, and our sales organization. To facilitate this support, the group must also interface with most of the design and development groups in the company. Responsibilities will involve working with Lattice's sale's organization to support customer hardware and software design issues. This will lead to involvement in the development of support related documentation, hardware and software.
Lattice is looking for an Entry Level Applications Engineer to join this team with the following responsibilities:
• Provide engineering and technical marketing support to field sales, field applications and customers.
• Support application hotline for specific product lines. Provide assistance to customers with technical problems.
• Conduct tests to evaluate customer problems.
• Generate and coordinate technical literature, articles, application notes and data sheets.
• Coordinate hardware failure verifications.
• Perform software benchmarking and competitive hardware analysis.
• Perform FPGA logic design using VHDL and Verilog.
• Provide follow-up support in disseminating technical information on specific applications.
Desired Candidate Profile
Qualifications:
• BTech/Mtech/ME/MSc in Electronics and Telecom or equivalent.
• Experience in digital logic design using FPGAs.
• Experience with VHDL and Verilog.
• Knowledge of C and C++.
• Understanding of telecom/datacom systems.
• Customer support experience preferred.
• Strong written and verbal communication skills and the ability to work with multiple groups.
• Must be detail oriented with strong customer service skills.
• High level of PC skills with knowledge of MS Office Suite.
• Experience in telecommunications, wireless and networking helpful.
• Experience with system design and applications engineering helpful.
Their total compensation package includes a comprehensive medical and dental insurance plan, 401K match, employee stock purchase plan and 3 weeks of vacation.
Company Profile
Lattice Semiconductor is one of the world's leading designers of programmable logic technology. NASDAQ-listed, with around 700 employees worldwide, our future has never looked more promising. We are an equal opportunity employer. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
For more information please visit
https://www4.ultirecruit.
Wednesday, April 14, 2010
Contract Verification Engineers
Design Verification Engineers, Contract opportunities in Texas and NorthEastern US. 3+ years industry experience. US residents or valid visa required.
Key Job Functions:
Develop environments for complex functional verification and debug both
functional and environmental errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design. Develop an automated regression infrastructure setup for functional verification of high speed processor type designs. Develop/run directed tests for current and new functional features and develop/use random excercisors, to validate functionality of processor type system designs. Debug regression fails at the RTL and gate level.
Software infrastructure for validation of architecture correctness.
Directed and Random functional test environment development and use
Experience with functional/power/performance verification using
simulation and emulation environments
Create test plans for complex IPs include multiple processors
Developing test benches in OVM, SystemVerilog and/or C++, applying
pseudo-random test generators, developing System Verilog/C/assembly tests,
analyzing coverage and design-for-test on next generation SOC chip
projects.
Knowledge with Verilog SystemVerilog, HDL, programming in Perl, C/C++,
logic simulation is a requirement. Direct experience with OVM simulation
environment is a strong plus. Knowledge of computer and peripheral
architectures is also required.
contact: Kathy@Xpeerant.com
Key Job Functions:
Develop environments for complex functional verification and debug both
functional and environmental errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design. Develop an automated regression infrastructure setup for functional verification of high speed processor type designs. Develop/run directed tests for current and new functional features and develop/use random excercisors, to validate functionality of processor type system designs. Debug regression fails at the RTL and gate level.
Software infrastructure for validation of architecture correctness.
Directed and Random functional test environment development and use
Experience with functional/power/performance verification using
simulation and emulation environments
Create test plans for complex IPs include multiple processors
Developing test benches in OVM, SystemVerilog and/or C++, applying
pseudo-random test generators, developing System Verilog/C/assembly tests,
analyzing coverage and design-for-test on next generation SOC chip
projects.
Knowledge with Verilog SystemVerilog, HDL, programming in Perl, C/C++,
logic simulation is a requirement. Direct experience with OVM simulation
environment is a strong plus. Knowledge of computer and peripheral
architectures is also required.
contact: Kathy@Xpeerant.com
Tuesday, April 6, 2010
Job Opportunity with US Based Product Development Company, Bangalore
Work as part of the Design Technology team to be part of development and support of digital IP designs to Product Company worldwide design teams. Primary responsibility includes build new digital IP components, support & maintenance of all digital IPs in the library, support design & implementation teams in different testchip programs in IP integration aspects.
Job functions include:
-Creation of verilog based RTL design, including micro-architecture definition and coding for DFT, synthesis rule compliance.
-Drive IP use model, revision control process and manage the IP release process to different design teams.
-Support bug fixes, design enhancements to keep all the IPs in library up-to-date.
-Work closely with verification team to ensure that exhaustive verification all IPs are done.
-Creating documentation to aid easy re-use of IP
-Work closely with the circuit, logic and implementation teams and support re-use & customization of IP.
Requirements:
-Bachelors or Masters in Electrical / Electronic Engineering with at least 3-4 years of experience in IP development and integration support.
-Hands on experience in Verilog based digital design creation.
-Prior memory technology (DDRx / GDDRx / LPDDRx) experience preferred.
-Exposure to scripting/programming ability using PERL, MAKEFILE.
-Good familiarity with usage of configuration management systems (any one of: DesignSync, ClearCase, Perforce, ICManage
-Hands on experience / support in tape-out of at least two chips would be added advantage.
Abilities:
-Work effectively and independently in a multi-site, multi-cultural environment
-Self-motivated team player with strong organizational, time management and communication skills.
Note: we will process your CV with your due Consent Only
Do send your Update CV & Please mention below details
Current CTC:
Expected CTC:
Duration for Joining:
Current Location:
Location Preference:
contact: nalini@techpointsolutions.com
Job functions include:
-Creation of verilog based RTL design, including micro-architecture definition and coding for DFT, synthesis rule compliance.
-Drive IP use model, revision control process and manage the IP release process to different design teams.
-Support bug fixes, design enhancements to keep all the IPs in library up-to-date.
-Work closely with verification team to ensure that exhaustive verification all IPs are done.
-Creating documentation to aid easy re-use of IP
-Work closely with the circuit, logic and implementation teams and support re-use & customization of IP.
Requirements:
-Bachelors or Masters in Electrical / Electronic Engineering with at least 3-4 years of experience in IP development and integration support.
-Hands on experience in Verilog based digital design creation.
-Prior memory technology (DDRx / GDDRx / LPDDRx) experience preferred.
-Exposure to scripting/programming ability using PERL, MAKEFILE.
-Good familiarity with usage of configuration management systems (any one of: DesignSync, ClearCase, Perforce, ICManage
-Hands on experience / support in tape-out of at least two chips would be added advantage.
Abilities:
-Work effectively and independently in a multi-site, multi-cultural environment
-Self-motivated team player with strong organizational, time management and communication skills.
Note: we will process your CV with your due Consent Only
Do send your Update CV & Please mention below details
Current CTC:
Expected CTC:
Duration for Joining:
Current Location:
Location Preference:
contact: nalini@techpointsolutions.com
Monday, March 15, 2010
Jobs @ Continuum, Newton, MA
Continuum (www.dcontinuum.com) in Newton, MA is looking for two people. Contact Adam Casey, acasey@dcontinuum.com:
** Software-Hardware Test Engineer **
This is a two-fold position. The candidate's primary responsibilities will be developing and performing all software testing, including unit tests using scripting languages. The candidate will oversee and execute the firmware/software quality process at Continuum, and have a central role in its ongoing refinement. He or she will be responsible for the verification and validation of embedded software and systems to detailed requirements. Knowledge of software test practices is a plus.
Secondary responsibilities will be electronic hardware design, including schematic capture, overseeing board layout and prototyping, hardware testing, and integration with firmware and mechanical systems.
B.S. in Electrical Engineering and 1-3 years experience digital hardware design experience.
** Embedded Systems Engineer II **
The candidate's primary responsibilities will be developing firmware and software for embedded applications. Platforms vary from small 8-bit microcontrollers to 32-bit microprocessors. Knowledge of real time operating systems and adherence to code standards and best practices are essential. Using oscilloscopes, digital multi-meters, function generators, and spectrum analyzers for debugging and development must be second-nature.
Secondary responsibilities will be development of software for non-embedded platforms. These may include web-based applications, desktop applications for various operating systems, or applications designed for mobile platforms.
Tertiary responsibilities may include electronic hardware design, schematic capture, overseeing board layout and prototyping, hardware testing, and integration with firmware and mechanical systems.
B.S. in Electrical Engineering and 2-4 years embedded firmware development experience.
** Software-Hardware Test Engineer **
This is a two-fold position. The candidate's primary responsibilities will be developing and performing all software testing, including unit tests using scripting languages. The candidate will oversee and execute the firmware/software quality process at Continuum, and have a central role in its ongoing refinement. He or she will be responsible for the verification and validation of embedded software and systems to detailed requirements. Knowledge of software test practices is a plus.
Secondary responsibilities will be electronic hardware design, including schematic capture, overseeing board layout and prototyping, hardware testing, and integration with firmware and mechanical systems.
B.S. in Electrical Engineering and 1-3 years experience digital hardware design experience.
** Embedded Systems Engineer II **
The candidate's primary responsibilities will be developing firmware and software for embedded applications. Platforms vary from small 8-bit microcontrollers to 32-bit microprocessors. Knowledge of real time operating systems and adherence to code standards and best practices are essential. Using oscilloscopes, digital multi-meters, function generators, and spectrum analyzers for debugging and development must be second-nature.
Secondary responsibilities will be development of software for non-embedded platforms. These may include web-based applications, desktop applications for various operating systems, or applications designed for mobile platforms.
Tertiary responsibilities may include electronic hardware design, schematic capture, overseeing board layout and prototyping, hardware testing, and integration with firmware and mechanical systems.
B.S. in Electrical Engineering and 2-4 years embedded firmware development experience.
Jobs @ Creston Electronics
Crestron Electronics, the world's leading manufacturer of advanced control and automation systems, is looking for talented embedded developers. We have been hiring Engineers steadily through the recent economic downturn and have in excess of 200 Engineers located in our brand new Research and Development Center in Rockleigh, NJ.
Are you a motivated embedded developer? Do you understand and work with Real Time OS's on a regular basis? Do you have experience with Nucleus, or Windows CE? Do you understand Ethernet network stacks? Zigbee networking? I2C, SPI and other hardware bus protocols?
We are hiring and all levels of experience!
Note: You must be legal to work in the United States without sponsorship.
If you want a great career in a thriving company developing leading edge products please send an email with the Subject: Firmware Developer Candidate, an introduction and your resume to: Careersnow@crestron.com.
For more information visit our website: www.Crestron.com
Are you a motivated embedded developer? Do you understand and work with Real Time OS's on a regular basis? Do you have experience with Nucleus, or Windows CE? Do you understand Ethernet network stacks? Zigbee networking? I2C, SPI and other hardware bus protocols?
We are hiring and all levels of experience!
Note: You must be legal to work in the United States without sponsorship.
If you want a great career in a thriving company developing leading edge products please send an email with the Subject: Firmware Developer Candidate, an introduction and your resume to: Careersnow@crestron.com.
For more information visit our website: www.Crestron.com
Jobs @ MaxLinear Inc., San Diego, CA
Three new positions at MAXLINEAR, INC in San Diego, CA, immediate hire,
full-time: Embedded developers (~5 years embedded development experience or focused M.S./Ph.D.) and Embedded Architect (~10+ years embedded development experience). Smaller & profitable fab-less semiconductor company in growth spurt. Good growth potential within the software team. Work on new wireless/broadband communication SoC's for consumer applications developed by in-house ASIC and RF team. Required: solid focus in firmware and low level debugging at pin level; C and assembly for RISC cores; multi-core/multi-processor systems; peripheral drivers and communication (USB/SPI/SDIO/TDM/I2C); Real-time operating systems; solid documentation and development system skills. Optional: DSP filtering, image processing, layer 2/3 protocols, GNU/Linux as embedded O/S, Win32 drivers. Email jcline@ieee.org for immediate response from the engineering team. **Include both resume and cover letter highlighting relevant prior projects, with the subject line: MAXLINEAR EMBEDDED.
full-time: Embedded developers (~5 years embedded development experience or focused M.S./Ph.D.) and Embedded Architect (~10+ years embedded development experience). Smaller & profitable fab-less semiconductor company in growth spurt. Good growth potential within the software team. Work on new wireless/broadband communication SoC's for consumer applications developed by in-house ASIC and RF team. Required: solid focus in firmware and low level debugging at pin level; C and assembly for RISC cores; multi-core/multi-processor systems; peripheral drivers and communication (USB/SPI/SDIO/TDM/I2C); Real-time operating systems; solid documentation and development system skills. Optional: DSP filtering, image processing, layer 2/3 protocols, GNU/Linux as embedded O/S, Win32 drivers. Email jcline@ieee.org for immediate response from the engineering team. **Include both resume and cover letter highlighting relevant prior projects, with the subject line: MAXLINEAR EMBEDDED.
Openings with ST Microelectronics, Greater Noida (India) - Memory Design
Verification & Circuit Design of Memory & Memory blocks
#Electronics Engg
#Exposure to CMOS fundamentals
#Exposure to VLSI design,
#Knowledge of design principles and practices,
#Good College Experience with circuit design, IC layout, UNIX scripts, and CAD verification, #Understanding of key SRAM blocks viz. Sense Amplifiers, Row Decoders, IOs etc, #Understanding of SRAM/ROM architecture,
#Understanding of semi-conductor design and manufacturing,
#Proficient in DRC/LVS/parasitic extraction/Spice simulations,
#Knowledgeable in design rule analysis, parasitic extraction, noise & crosstalk issues, yield improvement and manufacturability issues and design for test principles
B.Tech or M.Tech
1-8 yrs
#Electronics Engg
#Exposure to CMOS fundamentals
#Exposure to VLSI design,
#Knowledge of design principles and practices,
#Good College Experience with circuit design, IC layout, UNIX scripts, and CAD verification, #Understanding of key SRAM blocks viz. Sense Amplifiers, Row Decoders, IOs etc, #Understanding of SRAM/ROM architecture,
#Understanding of semi-conductor design and manufacturing,
#Proficient in DRC/LVS/parasitic extraction/Spice simulations,
#Knowledgeable in design rule analysis, parasitic extraction, noise & crosstalk issues, yield improvement and manufacturability issues and design for test principles
B.Tech or M.Tech
1-8 yrs
Job openings @ ST Microelectronics India - Analog PLL & EPM
To develop, support, qualify Analog IPs for embedded power management like - Thermal Sensor, voltage sensor, voltage Regulators, oscillators, low power scheme blocks
Looking for bright, enthusiastic engineers who can contribute dramatically in the field of Analog design with very strong fundamentals in Mathematics, Circuit theory, control systems & having deep understanding of VLSI issues. The person should have a strong Analytical mind and the ability to think out of the box to generate innovative ckts. The demanding work environment will encourage people to challenge the existing systems and to come out with leading solutions for today's VLSI industry. Project work includes: Thermal sensor, voltage sensor design,
Strong fundamentals in mathematical analysis of circuits, control systems. Prior experience in Voltage regulators, other power management blocks, oscillators, PLLs, ADCs, thermal sensor, voltage sensor is desirable
Btech, Mtech
3-7yrs
Looking for bright, enthusiastic engineers who can contribute dramatically in the field of Analog design with very strong fundamentals in Mathematics, Circuit theory, control systems & having deep understanding of VLSI issues. The person should have a strong Analytical mind and the ability to think out of the box to generate innovative ckts. The demanding work environment will encourage people to challenge the existing systems and to come out with leading solutions for today's VLSI industry. Project work includes: Thermal sensor, voltage sensor design,
Strong fundamentals in mathematical analysis of circuits, control systems. Prior experience in Voltage regulators, other power management blocks, oscillators, PLLs, ADCs, thermal sensor, voltage sensor is desirable
Btech, Mtech
3-7yrs
Job openings @ ST Microelectronics India - AMS Circuit Design
Responsibilities: As a team member of the team that is required to design, develop, test & support non-volatile memory macros & test-chips. The work includes full custom analog/mixed signal circuit design and layout, Digital design, CAD verification, silicon debug and documentation
Positive Attitude, Ability to work in uncertainties & dynamic environment, Problem Solving approach rather than fixing the blame, Ability to work hard in time of crisis, Good team work, Inclined to technical domain, High Analytical Skills, Sound fundamentals in Analog & Digital Electronics and microelectronics. Familiarity to CAD tools like OPUS, ELDO, HSIM
Knowledge of SRAM, DRAM, Flash memories; Experience in circuit design, Knowledge of VHDL/Verilog/C
B.Tech/M.Tech
1-2 years
Positive Attitude, Ability to work in uncertainties & dynamic environment, Problem Solving approach rather than fixing the blame, Ability to work hard in time of crisis, Good team work, Inclined to technical domain, High Analytical Skills, Sound fundamentals in Analog & Digital Electronics and microelectronics. Familiarity to CAD tools like OPUS, ELDO, HSIM
Knowledge of SRAM, DRAM, Flash memories; Experience in circuit design, Knowledge of VHDL/Verilog/C
B.Tech/M.Tech
1-2 years
Job openings @ ST Microelectronics India - Analog: HSL
Analog Design Engr: HighSpeedLink
Good Analog/Digital Ckt design fundamentals, CMOS process & Devices, Transmission Lines,
Schematic, Simulation, Layout finishing Knowledge;
High Speed Analog/SERDES designs,
Understanding of HDL, MATLAB;
Fast learner, innovative thinking.
B.Tech/M.Tech from IIT/Very Good Instt.
0-4yrs
Good Analog/Digital Ckt design fundamentals, CMOS process & Devices, Transmission Lines,
Schematic, Simulation, Layout finishing Knowledge;
High Speed Analog/SERDES designs,
Understanding of HDL, MATLAB;
Fast learner, innovative thinking.
B.Tech/M.Tech from IIT/Very Good Instt.
0-4yrs
Job openings @ ST Microelectronics India - HSL "Analog Specialist:
HighSpeedLink " "Experience in design of Analog & Mixed Signal, High-speed circuit, SERDES design.
Good experience of Schematic, Simulation, Layout finishing CAD tool usage.
Innovative thinking." "Knowledge of HDLs, MATLAB;
Exposer to High Speed Links: USB, HDMI, MIPI etc."
B.Tech/M.Tech from IIT/Very Good Instt.
3-7yrs
Good experience of Schematic, Simulation, Layout finishing CAD tool usage.
Innovative thinking." "Knowledge of HDLs, MATLAB;
Exposer to High Speed Links: USB, HDMI, MIPI etc."
B.Tech/M.Tech from IIT/Very Good Instt.
3-7yrs
Job openings @ ST Microelectronics India - HSL "Analog Architect:
HighSpeedLink " "Experience in architecting Analog & Mixed Signal, High-speed circuit, SERDES design.
Good experience of Schematic, Simulation, Layout finishing CAD tool usage. " "Knowledge of HDLs, MATLAB;
Exposer to High Speed Links: USB, HDMI, MIPI etc."
B.Tech/M.Tech/Ph.D. from IIT/Very Good Instt.
5-10yrs
2-5 yrs
Good experience of Schematic, Simulation, Layout finishing CAD tool usage. " "Knowledge of HDLs, MATLAB;
Exposer to High Speed Links: USB, HDMI, MIPI etc."
B.Tech/M.Tech/Ph.D. from IIT/Very Good Instt.
5-10yrs
2-5 yrs
Job openings @ ST Microelectronics India - Standard Cells
To design & develop circuits Layouts Views Chartersation & support Cad for Standard cell library design Knowledge of basic Circuit design, CMOS logic, Digital design. Programming skills, Knowledge verilog, VHDL
B.Tech
1-2 yrs
B.Tech
1-2 yrs
Job openings @ ST Microelectronics India - Test Engineer
Test Engineering for Analog & Mixed Signal Designs such as High Speed Links (USB, MIPI) and Data Converters.
The person should have hands-on experience on instrumentation such Oscilloscopes, LA, PG is a must. Experience on Validation of High Speed Links and/or Data Converters is a must. Knowledge on High Speed Board Design and LabView automation would be an added advantage
BE/ME
1-8 years
The person should have hands-on experience on instrumentation such Oscilloscopes, LA, PG is a must. Experience on Validation of High Speed Links and/or Data Converters is a must. Knowledge on High Speed Board Design and LabView automation would be an added advantage
BE/ME
1-8 years
Job openings @ ST Microelectronics India - Signal & Power Integrity
To Analyze High Speed Link Signal & Power Integrity, including external environment such as package, board & measuring instruments. Job includes analysis and optimization of external environment and the overall High Speed Link performance. The person should have analog/RF design orientation and strong technical background. Knowledge & experience on Signal & Power Integrity on High Speed Link devices is required. Experience on Agilent ADS, or equivalent tools, is an added advantage.
BE/ME/PhD
1-10 years
BE/ME/PhD
1-10 years
Job openings @ ST Microelectronics India - IOs Design
The incumbent will be required to work on IO designs to define and create standard and complex IO buffers (e.g. standard CMOS/TTL, DDR,LVDS, HSTL, SSTL, PCI, USB,LVTTL etc.) and work in various phases of the complete IO development cycle and silicon qualification (starting specification understanding, developing IOs, testchip implementation, review with designers, testchip simulations and verification, gds delivery, design verification on silicon) in VLSI nano technologies Strong Theoretical background and Analytical skills Clear understanding of basic electronics, MOS circuit design. Ability to work independently and within teams depending on project requirements Inquisitive and learning aptitude, ability to work under pressure Device physics Knowledge of ESD (electrstatic Discharge) and prevention techniques will be an additional plus
BE Electronics
2-5 years
BE Electronics
2-5 years
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Tuesday, March 9, 2010
Job openings @ Infineon India
- Experience in developing device drivers in mobile platform's.
- Experience with display, camera drivers and other graphics functionalities.
- Experience in developing device drivers in Linux environment preferably)
- Good understanding of Video Codec standards like MPEG-4, H.264, H.263.
- Exposure to RPC concepts.
Job openings @ Infineon India
- Exposure to different audio formats (Midi, Wav etc)
- Experience in speech codecs (AMR FR, AMR HR, HR, FR, EFR)
Job openings @ Infineon India
- Experience in RPC projects (Between processors)
- Experience in IPC drivers (UART, DPRAM, Shared RAM)
Job openings @ Infineon India
General
- ARM9 architecture knowledge
- Experience with RTOS (Preferably Nucleus)
- Experience in developing drivers for Mobile peripherals
- System debugging using Lauterbach debugger
- Programming skills in C and assembly
- Experience with clearcase
Job openings @ Infineon India
Architect
- 8 to 10+ years experience
- Solid background in embedded / software development
- Should have stayed in technical ladder or equivalent and not a project / people manager
- System wide experience in mobile device development with focus in any one area (2G/3G stack, device drivers, interfaces to applications etc)
- Exposure to "System Engineering" activities (interfacing to customers, Requirements collection, marketing, product management etc)
- Prior experience in hands-on devlopment with C / C++ in wireless domain, ARM based systems is preferred
- Exposure to customers is a plus
Thursday, March 4, 2010
Openings@Aruba Networks Bangalore(ASIC Verification Engineer )
ASIC Verification Engineer
We are looking for Verification Engineers who will be responsible for defining the test bench environment and contributing to the development of overall verification strategy, simulation environment, and coverage methodology. The candidate will work closely with a team of chip architects and digital design engineers.
Responsibilities include:
• Define pre-silicon verification/test plan.
• Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.
• Create and debug test case both in RTL and Gate Level simulation environment.
• Define and generate assertions and functional coverage points.
• Automate verification environment using Scripts.
• Create & analyze coverage metrics to ensure completeness.
REQUIREMENTS:
• BSEE, MSEE desired
• Minimum 5+ years of experience in ASIC design/verification
• Must possess at least 3 years work experience with SystemVerilog for verification.
• 3+ years of experience in both RTL and gate level verification and debug.
• Verification experience in the following product areas:
o High speed serial link (PCI-E, XAUI)
o DDR2/DDR3 memory controller
o High speed network or switching controller.
Please contact them directly!
Openings with US based Product Development Company, Bangalore
Techpoint solutions is a executive search firm working with Embedded / Datacomm / Networking / Telecom / Storage / Hardware / VLSI /Companies across cities in India. Currently they have Openings with US based Product Development Company, Bangalore
ASIC Verification:
We are looking for Verification Engineers who will be responsible for defining the test bench environment and contributing to the development of overall verification strategy, simulation environment, and coverage methodology. The candidate will work closely with a team of chip architects and digital design engineers.
Responsibilities include:
- Define pre-silicon verification/test plan.
- Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.
- Create and debug test case both in RTL and Gate Level simulation environment.
- Define and generate assertions and functional coverage points.
- Automate verification environment using Scripts.
- Create & analyze coverage metrics to ensure completeness.
REQUIREMENTS:
- BSEE, MSEE desired
- Minimum 5+ years of experience in ASIC design/verification
- Must possess at least 3 years work experience with SystemVerilog for verification.
- 3+ years of experience in both RTL and gate level verification and debug.
- Verification experience in the following product areas:
- High speed serial link (PCI-E, XAUI)
- DDR2/DDR3 memory controller
- High speed network or switching controller. .
- Current CTC:
- Expected CTC:
- Duration for Joining:
- Current Location:
ASIC, Verification, Methodology and Analog Circuit Engineers. (Multiple positions)
I am working with a San Jose, CA Company that is looking for ASIC, Verification, Methodology and Analog Circuit Engineers. (Multiple positions) These are full-time employment opportunities.
Location
San Jose, CA
San Jose, CA
Company
Our client develops and sells, ICs that enable 10 Gigabit transmissions over standard copper cable. As the need for high bandwidth continues to increase, our client is positioned to grow.
Our client develops and sells, ICs that enable 10 Gigabit transmissions over standard copper cable. As the need for high bandwidth continues to increase, our client is positioned to grow.
ASIC Design
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_IC_design
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_IC_design
ASIC Design Verification
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_IC_design_verification
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_IC_design_verification
ASIC Design Methodology
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_ASIC
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_ASIC
Analog Mixed-Signal Design
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_analog
http://ctsearch.com/opportunities/opportunities_detail.html#hardware_development_analog
If you know someone that would be a good fit, please forward this email to them.
Do not hesitate to contact me if you have any additional questions or send me an updated resume if you are interested.
Sandy Perlman
Principal & Sr. Recruiter, BSEE
http://www.ctsearch.com/
sandyperlman@ctsearch.com
www.twitter.com/sandyperlman
www.linkedin.com/in/sandyperlman
Principal & Sr. Recruiter, BSEE
http://www.ctsearch.com/
sandyperlman@ctsearch.com
www.twitter.com/sandyperlman
www.linkedin.com/in/sandyperlman
Job Request: VLSI based Jobs
Dear Hiring Manager,
I would like to express my interests in applying for the Full-time/contract position in the field of Electrical Engineer.
I am a recently college graduate(Masters Degree) in Electrical Engineering at California State University, Sacramento. During first semester of my graduate studies, I have taken courses -Analog and Mixed Design Integrated Circuits, CMOS and VLSI, Advanced Logic Design. Analysis of Analog and Digital system design have given me an in-depth knowledge of digital aspects of designs. Projects in Analog Circuits, Digital Design, CMOS and VLSI have exposed me to the circuits requirements, designing the simple circuits using PSpice Tool, coding programs in Verilog and VHDL for different Lab projects , CMOS layout, CMOS circuit design, basic VLSI layouts using L-edit Tool to design a project.
In the Second and Third Semesters I have taken Micro Computer System Design, Advanced timing analysis, Advanced VLSI Design for Test, Fiber Optic Communications, Power Economic Dispatch courses. Micro Computer System Design has given me a fair exposure to PCI /PCI Express Architecture , the course work exposed to the bus timings arbitrations and multi-factors that must be kept in mind when designing for a bus. Advanced Timing Analysis has taught me TCL scripting, static timing analysis, clock timing issues, timing exceptions, operating conditions . Advanced VLSI Design for Test exposed me to to IC design for test techniques, Semiconductor Fabrication process. The projects have taught me professional way of presentations and documentations. Course Projects in detail are included in resume.
My courses and various course projects have helped me to put relevant skills and knowledge into practice some of the strengths that I can offer include being a hard worker eager and willing to learn. I have ability to achieve results in demanding situations. I am confident that my qualifications and experience match the skills you look for in an Intern and I can be a valuable asset to your team. I am a Indian National and thinking to come back and work for in India . I would appreciate if you can arrange an appointment so that we can discuss more about my experience and the skills. I am attaching a resume with this mail for your kind perusal. Thank you for your consideration.
Best Regards,
Vakula Peesari
Address : 508 Pine Garden Lane, #F Sacramento, CA 95825 Email: mailto:vakulapeesari@gmail.com
Contact Number: 916-221-1715
Sunday, February 7, 2010
Optimization/Process Engineer
The Cooper River Plant is located on the U.S. east coast, about 15 miles north of Charleston, South Carolina, and is home to one of the world's largest single purified terephthalic acid (PTA) units. PTA is the preferred intermediate used in the manufacture of polyester resin for fibers, films, and packaging. The plant has two production units and associated shipping, utility and waste treatment facilities. The facility is set on 5,900 acres with nearly one-third consisting of wetlands.
The Process Engineer will be responsible for unit troubleshooting, process engineering support and capital projects required to sustain and improve unit operations.
Qualifications:
• A minimum of Bachelor's degree in chemical engineering.
• A minimum of 4 years of experience as a Chemical Engineer working in a chemical plant, refinery or equivalent.
• Proficient experience with troubleshooting process equipment and associated piping instruments (heat exchangers, pumps, vessels, compressors, etc.).
• Performance Bias - Focuses effort and prioritises work to deliver business value - Skillful
• Performance Bias - Bias for action - does things before being asked to or forced to by events - Skillful
• Taking the lead - Uses a range of styles to influence and gain enrolment - Skillful
• Partnership and Teamworking - Builds networks to enhance effectiveness and share knowledge - Skillful
• Partnership and Teamworking - Actively engages and respects contributions of others, in face to face or virtual meetings - Skillful
• Wise Decisions - Progresses issues, even when only partial information is available - Skillful
• Wise Decisions - Considers the merits of differing positions or opposing viewpoints - Skillful
• Innovation - Thinks outside normal limits, takes unusual perspectives, challenges traditional thinking - Skillful
Our business is the exploration, production, refining, trading and distribution of energy. This is what we do, and we do it on a truly global scale. With a workforce of nearly 100,000 employees, BP operates with business activities and customers in more than 100 countries across six continents. Every day, we serve millions of customers around the world. We are continually looking for talented, committed and ambitious people to help us shape the face of energy for the future.
The Aromatics and Acetyls strategic performance unit (A&A SPU) sits within the Refining and Marketing segment of the BP Group. It is a global manufacturing and marketing petrochemicals business, with operations in Asia, Europe and the US. Globally our Aromatics and Acetyls productions have leading proprietary technology in these areas, and benefit from strong positions in the established US and European markets and the growing Asian markets.
The A&A business comprises manufacturing sites in the US, Europe and Asia. There are 6 wholly-owned manufacturing sites in the US, Belgium, United Kingdom and Malaysia, and 7 joint-venture manufactory sites in China, Indonesia, Korea, Malaysia and Taiwan. Specifically, Asia centered on China is the focal and strategic development region for A&A business.
If you are selected for the position, your employment will be contingent upon submission to and successful completion of a post-offer/pre-placement drug and alcohol screening as well as pre-placement verification of the information and qualifications provided during the selection process.
BP is an equal opportunity employer.
Apply URL: http://posttrak.arbita.net/cgi-bin/PostTrak.cgi?RefCode=R1830220408129
The Process Engineer will be responsible for unit troubleshooting, process engineering support and capital projects required to sustain and improve unit operations.
Qualifications:
• A minimum of Bachelor's degree in chemical engineering.
• A minimum of 4 years of experience as a Chemical Engineer working in a chemical plant, refinery or equivalent.
• Proficient experience with troubleshooting process equipment and associated piping instruments (heat exchangers, pumps, vessels, compressors, etc.).
• Performance Bias - Focuses effort and prioritises work to deliver business value - Skillful
• Performance Bias - Bias for action - does things before being asked to or forced to by events - Skillful
• Taking the lead - Uses a range of styles to influence and gain enrolment - Skillful
• Partnership and Teamworking - Builds networks to enhance effectiveness and share knowledge - Skillful
• Partnership and Teamworking - Actively engages and respects contributions of others, in face to face or virtual meetings - Skillful
• Wise Decisions - Progresses issues, even when only partial information is available - Skillful
• Wise Decisions - Considers the merits of differing positions or opposing viewpoints - Skillful
• Innovation - Thinks outside normal limits, takes unusual perspectives, challenges traditional thinking - Skillful
Our business is the exploration, production, refining, trading and distribution of energy. This is what we do, and we do it on a truly global scale. With a workforce of nearly 100,000 employees, BP operates with business activities and customers in more than 100 countries across six continents. Every day, we serve millions of customers around the world. We are continually looking for talented, committed and ambitious people to help us shape the face of energy for the future.
The Aromatics and Acetyls strategic performance unit (A&A SPU) sits within the Refining and Marketing segment of the BP Group. It is a global manufacturing and marketing petrochemicals business, with operations in Asia, Europe and the US. Globally our Aromatics and Acetyls productions have leading proprietary technology in these areas, and benefit from strong positions in the established US and European markets and the growing Asian markets.
The A&A business comprises manufacturing sites in the US, Europe and Asia. There are 6 wholly-owned manufacturing sites in the US, Belgium, United Kingdom and Malaysia, and 7 joint-venture manufactory sites in China, Indonesia, Korea, Malaysia and Taiwan. Specifically, Asia centered on China is the focal and strategic development region for A&A business.
If you are selected for the position, your employment will be contingent upon submission to and successful completion of a post-offer/pre-placement drug and alcohol screening as well as pre-placement verification of the information and qualifications provided during the selection process.
BP is an equal opportunity employer.
Apply URL: http://posttrak.arbita.net/cgi-bin/PostTrak.cgi?RefCode=R1830220408129
Wednesday, February 3, 2010
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