Showing posts with label RTL. Show all posts
Showing posts with label RTL. Show all posts

Saturday, April 23, 2011

AMD, Bangalore: RTL Designer

This job involves:
• Developing micro-architecture of high speed cache memories in an x86 based CPU
• Drive key aspects of block specification (timing, area, power, clocking, BIST/DFT etc.)
• Opportunity in micro architecture and architecture innovation
• RTL development for respective blocks
• Synthesize RTL per timing/area constraints
• Responsible for closing on logical equivalence (LEC) of gates vs. RTL
• Responsible for functional equivalence of arrays via symbolic simulators or LEC tools
• Manage IP dependencies, planning and tracking of all RTL related tasks

Qualifications:
• BE/MS with 10 years of relevant experience
• Proven track record in micro-architecture / RTL development
• Familiarity with memory system architectures like caches, coherence, controllers
• Solid understanding of BIST, DFT, Repair architectures for memories
• Familiarity with x86 architecture is a big plus
• Experienced in RTL debug, verification (like setting up test benches etc.)
• Experience with synthesis and static timing tools
• Well versed in Verilog/VHDL, running regressions and other RTL related tools etc.
• Well versed with LEC based tools like Verplex or Innologic
• Excellent communication and leadership skills, cross site experience is a plus

Send resumes to jobin.sathiadas@careernet.co.in

Wednesday, September 29, 2010

Design & Verification

· 3-10 years of experience in Verilog/VHDL design, analysis and verification of DSP functions
· Developing block level micro-architecture of DSP blocks from algorithms specified in C
· Use HDL for logic design; perform synthesis, static timing analysis & power estimation of the design
· Create self generating / self checking simulation verification environment using C, HDL, Perl scripts
· Be familiar with Verilog and Synopsys tools (VCS, DC, Power Compiler)
· Successful experience in 802.11 Wireless VLSI designs or other related technologies is a plus
· Education: BE/Btech/ME/MTech

Contact:
For more details please contact, Asesh @ 9916784464, E-mail: v.asesh@neweraindia.com

Tuesday, April 6, 2010

Job Opportunity with US Based Product Development Company, Bangalore

Work as part of the Design Technology team to be part of development and support of digital IP designs to Product Company worldwide design teams. Primary responsibility includes build new digital IP components, support & maintenance of all digital IPs in the library, support design & implementation teams in different testchip programs in IP integration aspects.

Job functions include:
-Creation of verilog based RTL design, including micro-architecture definition and coding for DFT, synthesis rule compliance.
-Drive IP use model, revision control process and manage the IP release process to different design teams.
-Support bug fixes, design enhancements to keep all the IPs in library up-to-date.
-Work closely with verification team to ensure that exhaustive verification all IPs are done.
-Creating documentation to aid easy re-use of IP
-Work closely with the circuit, logic and implementation teams and support re-use & customization of IP.

Requirements:
-Bachelors or Masters in Electrical / Electronic Engineering with at least 3-4 years of experience in IP development and integration support.
-Hands on experience in Verilog based digital design creation.
-Prior memory technology (DDRx / GDDRx / LPDDRx) experience preferred.  
-Exposure to scripting/programming ability using PERL, MAKEFILE.
-Good familiarity with usage of configuration management systems (any one of: DesignSync, ClearCase, Perforce, ICManage
-Hands on experience / support in tape-out of at least two chips would be added advantage.

Abilities:
-Work effectively and independently in a multi-site, multi-cultural environment
-Self-motivated team player with strong organizational, time management and communication skills.

Note: we will process your CV with your due Consent Only
Do send your Update CV & Please mention below details

Current CTC:
Expected CTC:
Duration for Joining:
Current Location:
Location Preference:

contact: nalini@techpointsolutions.com