ST Ericsson: Front end IC design/verification

Min. Qualifications:
• M.Tech / Masters degree or equivalent
• VLSI/ASIC design and verification experience
• Work experience: 8-15 years

Optional but nice to have one or more following experiences:
• Design experience in ARM systems with AMBA buses
• Verification techniques – constrained random, assertion based
• Design For Test for SoCs – ATPG, scan
• Analog/Digital Mixed-signal block verification – Verilog AMS

Send resumes to jobin.sathiadas@careernet.co.in

AMD, Bangalore: RTL Designer

This job involves:
• Developing micro-architecture of high speed cache memories in an x86 based CPU
• Drive key aspects of block specification (timing, area, power, clocking, BIST/DFT etc.)
• Opportunity in micro architecture and architecture innovation
• RTL development for respective blocks
• Synthesize RTL per timing/area constraints
• Responsible for closing on logical equivalence (LEC) of gates vs. RTL
• Responsible for functional equivalence of arrays via symbolic simulators or LEC tools
• Manage IP dependencies, planning and tracking of all RTL related tasks

Qualifications:
• BE/MS with 10 years of relevant experience
• Proven track record in micro-architecture / RTL development
• Familiarity with memory system architectures like caches, coherence, controllers
• Solid understanding of BIST, DFT, Repair architectures for memories
• Familiarity with x86 architecture is a big plus
• Experienced in RTL debug, verification (like setting up test benches etc.)
• Experience with synthesis and static timing tools
• Well versed in Verilog/VHDL, running regressions and other RTL related tools etc.
• Well versed with LEC based tools like Verplex or Innologic
• Excellent communication and leadership skills, cross site experience is a plus

Send resumes to jobin.sathiadas@careernet.co.in

Broadcom: Engineer, Principal - IC Design

Job Description
1. 12+ years with BSEE or 9+ years with MSEE of experience in frontend VLSI design
2. Must have worked on complex SoC/IP block designs and proficient in verilog coding.
3. Excellent micro-architecture and Logic design
4. Good understanding of SoC/CPU subsystem
5. Experience related to AXI, PCIe, USB3.0, SDIO3, DDR3, NAND Flash is desirable.
6. Should have good documentation/communication and analytical skills and should be able to work with multi-functional, multi-site teams
7. Self motivated and independent contributor

Send resumes to jobin.sathiadas@careernet.co.in

Job Requirements
1. 12+ years with BSEE or 9+ years with MSEE of experience in frontend VLSI design
2. Must have worked on complex SoC/IP block designs and proficient in verilog coding.
3. Excellent micro-architecture and Logic design
4. Good understanding of SoC/CPU subsystem
5. Experience related to AXI, PCIe, USB3.0, SDIO3, DDR3, NAND Flash is desirable.
6. Should have good documentation/communication and analytical skills and should be able to work with multi-functional, multi-site teams
7. Self motivated and independent contributor

VLSI - Physical Design Engineer - 1 to 10 years, Bangalore / Hyderabad

Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)

Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout

Clear understanding and command over all aspects of physical design

Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter

Skill and experience in scripting using Tcl or Perl desirable.

Work Location : Hyderabad / Bangalore

Mail your resume to silu@roljobs.com with current and expected salary

SALARY WILL NOT BE A CONSTRAINT FOR THE RIGHT CANDIDATE