Job Description: IP verification MTS Engineer is responsible to lead the Pre Silicon verification team for the timely delivery the good Quality of RTL and Gates to the consumers and also work on design Enhancements and methodology improvements to upgrade the Quality metrics.
Job Responsibilities:
This candidate is responsible to lead a verification team for an IP block and closely working with Design/Architecture/Circuit team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery. He/She would be reviewing the day-day team’s activities on developing verification test bench activities such as feature scoping, test case development, Infrastructure enhancements, coverage and debug efforts. He/She will also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment. Also driving and participating pre silicon Verification discussions across other functional engineering team geographically.
Relevant Experience:
- BE/B.Tech with 8 to 12 years of experience or M.E/M.Tech with 6 to 10 years of experience in Pre silicon verification out of which 3 years in Technical leadership position.
- Minimum 6 years of relevant experience in RTL Verification of complex logic blocks in processor, chipset, networking domain is essential.
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification.
- Needs to have better understanding of Verification methodology and concepts.
- Should have excellent communication skills (both written and oral) and should be able to participate and drive cross functional engineering teams geographically.
- Must have worked in verification of few multi-million gate projects either at unit , cluster or top level.
- Must have better programming knowledge on Verilog,C++.
- Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
- Knowledge of memory controller (along with domain knowledge of DDR) sub-system is a desirable.(for DDR)
- Analog design knowledge such as transistors, circuit models are desirable. Should have better understanding of Gatesim, Nanasim tools and methodology (for AMS).
Contact: rajsree@techpointsolutions.com
