ST Ericsson: Front end IC design/verification

Min. Qualifications:
• M.Tech / Masters degree or equivalent
• VLSI/ASIC design and verification experience
• Work experience: 8-15 years

Optional but nice to have one or more following experiences:
• Design experience in ARM systems with AMBA buses
• Verification techniques – constrained random, assertion based
• Design For Test for SoCs – ATPG, scan
• Analog/Digital Mixed-signal block verification – Verilog AMS

Send resumes to jobin.sathiadas@careernet.co.in

MTS Engineer- AMSCOE Verification

Job Description:  IP verification MTS Engineer is responsible to lead the Pre Silicon verification team for the timely delivery the good Quality of RTL and Gates to the consumers and also work on design Enhancements and methodology improvements to upgrade the Quality metrics. 

Job Responsibilities: 

This candidate is responsible to lead a verification team for an IP block and closely working with Design/Architecture/Circuit team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery. He/She would be reviewing the day-day team’s activities on developing verification test bench activities such as feature scoping, test case development, Infrastructure enhancements, coverage and debug efforts. He/She will also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment. Also driving and participating pre silicon Verification discussions across other functional engineering team geographically.

 Relevant Experience:

• BE/B.Tech with 8 to 12 years of experience or M.E/M.Tech with 6 to 10 years of experience in Pre silicon verification out of which 3 years in Technical leadership position.
• Minimum 6 years of relevant experience in RTL Verification of complex logic blocks in processor, chipset, networking domain is essential.
• Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification.
• Needs to have better understanding of Verification methodology and concepts.
• Should have excellent communication skills (both written and oral) and should be able to participate and drive cross functional engineering teams geographically.
• Must have worked in verification of few multi-million gate projects either at unit , cluster or top level.
• Must have better programming knowledge on Verilog,C++.
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Knowledge of memory controller (along with domain knowledge of DDR) sub-system is a desirable.(for DDR)
• Analog design knowledge such as transistors, circuit models are desirable. Should have better understanding of Gatesim, Nanasim tools and methodology (for AMS).

Contact: rajsree@techpointsolutions.com

Design & Verification

· 3-10 years of experience in Verilog/VHDL design, analysis and verification of DSP functions
· Developing block level micro-architecture of DSP blocks from algorithms specified in C
· Use HDL for logic design; perform synthesis, static timing analysis & power estimation of the design
· Create self generating / self checking simulation verification environment using C, HDL, Perl scripts
· Be familiar with Verilog and Synopsys tools (VCS, DC, Power Compiler)
· Successful experience in 802.11 Wireless VLSI designs or other related technologies is a plus
· Education: BE/Btech/ME/MTech

Contact:
For more details please contact, Asesh @ 9916784464, E-mail: v.asesh@neweraindia.com

Contract Verification Engineers

Design Verification Engineers, Contract opportunities in Texas and NorthEastern US. 3+ years industry experience. US residents or valid visa required.

Key Job Functions:
Develop environments for complex functional verification and debug both
functional and environmental errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design. Develop an automated regression infrastructure setup for functional verification of high speed processor type designs. Develop/run directed tests for current and new functional features and develop/use random excercisors, to validate functionality of processor type system designs. Debug regression fails at the RTL and gate level.
Software infrastructure for validation of architecture correctness.
Directed and Random functional test environment development and use
Experience with functional/power/performance verification using
simulation and emulation environments
Create test plans for complex IPs include multiple processors
Developing test benches in OVM, SystemVerilog and/or C++, applying
pseudo-random test generators, developing System Verilog/C/assembly tests,
analyzing coverage and design-for-test on next generation SOC chip
projects.
Knowledge with Verilog SystemVerilog, HDL, programming in Perl, C/C++,
logic simulation is a requirement. Direct experience with OVM simulation
environment is a strong plus. Knowledge of computer and peripheral
architectures is also required.

contact: Kathy@Xpeerant.com

Openings@Aruba Networks Bangalore(ASIC Verification Engineer )

ASIC Verification Engineer

We are looking for Verification Engineers who will be responsible for defining the test bench environment and contributing to the development of overall verification strategy, simulation environment, and coverage methodology. The candidate will work closely with a team of chip architects and digital design engineers.

Responsibilities include:

• Define pre-silicon verification/test plan.

• Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.

• Create and debug test case both in RTL and Gate Level simulation environment.

• Define and generate assertions and functional coverage points.

• Automate verification environment using Scripts.

• Create & analyze coverage metrics to ensure completeness.

REQUIREMENTS:

• BSEE, MSEE desired

• Minimum 5+ years of experience in ASIC design/verification

• Must possess at least 3 years work experience with SystemVerilog for verification.

• 3+ years of experience in both RTL and gate level verification and debug.

• Verification experience in the following product areas:

o High speed serial link (PCI-E, XAUI)

o DDR2/DDR3 memory controller

o High speed network or switching controller.

Please contact them directly!

Openings with US based Product Development Company, Bangalore

Techpoint solutions is a executive search firm working with Embedded / Datacomm / Networking / Telecom / Storage / Hardware / VLSI /Companies across cities in India.  Currently they have Openings with US based Product Development Company, Bangalore

ASIC Verification:

We are looking for Verification Engineers who will be responsible for defining the test bench environment and contributing to the development of overall verification strategy, simulation environment, and coverage methodology. The candidate will work closely with a team of chip architects and digital design engineers.

Responsibilities include:

• Define pre-silicon verification/test plan.
• Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.
• Create and debug test case both in RTL and Gate Level simulation environment.
• Define and generate assertions and functional coverage points.
• Automate verification environment using Scripts.
• Create & analyze coverage metrics to ensure completeness.

REQUIREMENTS:

• BSEE, MSEE desired
• Minimum 5+ years of experience in ASIC design/verification
• Must possess at least 3 years work experience with SystemVerilog for verification.
• 3+ years of experience in both RTL and gate level verification and debug.
• Verification experience in the following product areas:
• High speed serial link (PCI-E,  XAUI)
• DDR2/DDR3 memory controller
• High speed network or switching controller. .

Do send your Update CV to nalini@techpointsolutions.com & Please mention below details

• Current CTC:
• Expected CTC:
• Duration for Joining:
• Current Location: